1. Field of the Invention
The present invention relates to electronic devices, and in particular, to memory electronic devices.
2. Description of Related Art
Most common dynamic, random-access memories (DRAMs) cells store charge on a capacitor and use a single transistor for accessing the capacitor. More recently, a memory cell has been proposed which stores charge in a floating body of a transistor. In this memory cell, a back gate is biased to retain charge in the floating body. An oxide layer is formed on a silicon substrate and a silicon layer for the active devices is formed on the oxide layer. The silicon substrate is used as the back gate, and consequently, must be biased relative to the silicon layer. Unfortunately, the oxide layer is relatively thick, requiring a relatively high voltage for the bias. Several gate structures have been proposed to reduce this relatively high bias potential, including use of a double gate, a split-gate and silicon pillars. The double gate and silicon pillar structures are relatively difficult to fabricate.
Referring to FIG. 1, a double-gate, floating-body memory cell or transistor 10 is illustrated. The memory cell 10 is formed on a P-doped substrate 12 and includes an active region comprising an N+ type source 14, an N+ type drain 16, and a P type channel 18. The memory cell 10 further includes an N+ type front gate 20 disposed on one side of the channel 18 and a P+ type back gate 22 formed in a buried oxide layer 24 disposed on the other side of the channel 18. The buried oxide layer 24 is formed on top of the P-type silicon substrate 12. The active region is formed of silicon. A dynamic, random-access memory (DRAM) is formed from a memory array (not shown) of the memory cells 10. The memory array has rows of different word-lines formed by a plurality of interconnected front gates 20 of individual cells 10 and columns of different bit lines coupled to a plurality of drains 16 of individual cells 10 along each bit line, with all of the sources 14 of the cells 10 being commonly coupled.
The threshold voltage of the memory cell 10 is programmable or adjustable, based upon the charge stored on the back gate 22. The back gate 22 is used to create a potential where holes may accumulate. More specifically, a state “1” and a state “0” may be associated with charges and with no charges, respectively, being stored on the back gate 22. For the state “1”, the back gate 22 is biased at a voltage to retain the charges. For the state “0”, due to junction leakages, charges eventually build up in the back gate 22, making the state “0” indistinguishable from the state “1.” Hence, the memory cell 10 needs to be periodically refreshed at sufficiently frequent intervals to avoid the states from becoming indistinguishable. The “retention time” may be defined as the time permitted between refreshing the back gate 22 before the state “0” is lost. The retention time of silicon may be longer than 1 second at room temperature. However, the retention time is degraded by more than 300 times from room temperature to 110 degrees C. due to the small energy bandgap in silicon. The retention time can be further reduced with small memory cells 10 due to surface defects. In summary, the retention time difficulty is an intrinsic problem of silicon; hence, application of a silicon-based memory cell 10 to sub-100 nm devices may be marginal.
Fabrication of the back gate 22 creates another difficulty with the floating body memory cell 10. Electrical contacts to the back gate 22 still take up quite a bit of cell area. The letter “F” designates the minimum line width of a feature size that may be patterned with lithography. The contacts to the back gate 22 prevent the memory cell 10 from having a cell memory area of 4 F2.
To fabricate the memory cell 10, Silicon-on-Insulator (SOI) technology is used. Fabrication starts with a lightly doped silicon wafer having an insulating silicon dioxide (SiO2) layer 24, i.e., buried oxide layer, formed by use a SIMOC (Separation by Implantation of Oxygen) process or a BESOI (BondEd SOI) process. This creates a thin layer of silicon above the buried oxide layer 24 and a thick layer underneath which forms the P-substrate 12. The active region (source 14, drain 16, and channel 18) of the memory cell 10 is constructed on the thin layer of silicon above the buried oxide layer 24.
Silicon carbide (SiC)-on-insulator wafers have been made. MOS and bipolar devices have been made on a silicon carbide crystal for power applications and non-volatile memory. MOS and bipolar devices also have been demonstrated with silicon carbide-on-silicon (SiC-on-Si) materials.